Today mainly introduced as one of the connector manufacturers manufacturing process - the development of packaging technology, electronic connectors to introduce a variety of packages and connector packaging considerations. The package is mainly divided into two DIP DIP and SMD chip package.

First, the development of packaging history

The package has undergone the following development process:

Structural aspects: TO-> DIP-> PLCC-> QFP-> BGA-> CSP;

Materials: metal, ceramic -> ceramic, plastic -> plastic;

Pin Shape: Long Leads Inline -> Short Leads or Leadless Mounting -> Ball Bumps;

Assembly methods: Through-hole cartridge -> Surface assembly -> Direct installation

Second, an important measure of a chip packaging technology is an important indicator of the chip area and package area ratio, the ratio closer to 1 the better. The main considerations when packaging:

1, chip area and package area ratio to improve packaging efficiency, as close to 1: 1;

2, the pin as short as possible to reduce the delay, the distance between the pins as far as possible to ensure non-interference and improve performance;

3, based on the cooling requirements, the thinner the better packaging

Third, the specific package

1, SOP / SOIC package

SOP is the abbreviation of English Small Outline Package, namely small outline package. SOP packaging technology developed by Philips in 1968 ~ 1969, then gradually derived SOJ (J pin small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP SOP), TSSOP (Thin SOP), SOT (Small Outline Transistor), SOIC (Small Outline Integrated Circuit) and the like.

2, DIP package

DIP is English Double In-line Package acronym, that is dual in-line package. One of the plug-in package, the pin leads from both sides of the package, the package material is plastic and ceramic two. DIP is the most popular plug-in package, applications include standard logic IC, memory LSI, microcomputer circuits.

3, PLCC package

PLCC is an acronym for English Plastic Leaded Chip Carrier, plastic J lead chip package. PLCC package, the shape was square, 32-pin package, all around the pin, the outline size is much smaller than the DIP package. PLCC package suitable for SMT surface mount technology to install wiring in the PCB, with small size, high reliability advantages.

4, TQFP package

TQFP is an English abbreviation for thin quad flat package, that is, a thin plastic package quad flat package. The quad flat package (TQFP) process enables efficient use of space, reducing the need for space on the printed circuit board. Due to reduced height and volume, this packaging process is ideal for space-demanding applications such as PCMCIA cards and networking devices. Almost all ALTERA CPLDs / FPGAs have TQFP packages.

5, PQFP package

PQFP is the abbreviation of Plastic Quad Flat Package in English, that is, plastic quad flat package. PQFP package chip distance between the pins is small, the pin is very thin, general large-scale or very large scale integrated circuits using this package, the pin number is generally more than 100.

6, TSOP package

TSOP is an abbreviation of English Thin Small Outline Package, that is, a small and small size package. A typical feature of TSOP memory packaging technology is the pin-outs around the packaged chips that are suitable for mounting on PCB (printed circuit board) using SMT technology (surface mount technology). TSOP package dimensions, parasitic parameters (large current changes, causing the output voltage disturbance) to reduce for high-frequency applications, more convenient operation, reliability is relatively high.

7, BGA package

BGA English Ball Grid Array Package acronym, the ball grid array package.